In order to mount semiconductor devices or components such as chipsets as many as possible on a limited area of a mother board, a variety of stacked-chip package such as S-CSP (Stacked Chip Scale Package) and S-MCP (Multi Chip Package) have been provided in the art. Typically, the package includes a daughter board to be positioned on the mother board and one or stacked plural semiconductor chips mounted on either or both surfaces of the daughter board.
FIGS. 11 and 12 illustrate an example of the conventional stacked package (S-CSP) generally indicated by reference numeral 100. The package 100 includes a daughter board in the form of circuit board 102. The circuit board 102 is wired on its top surface with an electric circuit including a plurality of connection pads or bonding pads 104(1041–1045) and is provided on its bottom surface with a number of solder balls 106 corresponding to the bonding pads 104, so that each pair of bonding pad 104 and solder ball 106 is electrically connected through a corresponding through-hole 108 formed in the circuit board 102. The circuit board 102 bears first and second semiconductor chips 110 and 112 manufactured through a well-known semiconductor manufacturing process and stacked in this order on the top surface of the circuit board 102. The first semiconductor chip 110 has bonding pads 114 (1142, 1144) electrically connected with circuit elements formed in the chip. The second semiconductor chip 112 on the other hand includes another bonding pads 114 (1141, 1143, 1145) electrically connected with electric elements formed in the chip. The bonding pads of the first and second semiconductor chips 110 and 112 are arranged so that, when viewed from the Y-Y direction, the bonding pad 1142 positions between the bonding pads 114, and 1143 and the bonding pad 1144 positions between the bonding pads 1143 and 1145. Also, the bonding pads 1141–1145 are electrically connected with the corresponding bonding pads 104 (1041–1045) mounted on the circuit board 102 through respective gold bonding wires. Then, the circuit board 102 with the first and second semiconductor chips 110 and 112 so constructed is sealed by a suitable resin so that the resin covers the chips 110 and 112 and boding wires 116. Thereby, the semiconductor device is completed. It should be noted that the commercially available semiconductor device includes more bonding pads on the circuit board and/or the first and second semiconductor chips; however, only a part of which is illustrated in FIGS. 10 and 11 for the clarification of those drawings.
The above-described semiconductor device 100 in which the semiconductor chips 110 and 112 are electrically connected with the circuit board 102 through bonding pads 104 and 114 mounted thereon and bonding wires 116 extending between corresponding bonding pads requires the bonding pads 1141–1045 of the semiconductor chips 110 and 112 and bonding pads 1041–1045 of the circuit board 102 to be arranged in this order in the X–X′ direction, respectively. Specifically, as shown in FIG. 12, the five bonding pads 1041–1045 aligned in the X–X′ direction on the circuit board 102 should be related with the bonding pads 1141–1145 on the semiconductor chips 110 and 112. This is because that, when assuming that the bonding pad 1045 on the circuit board 102 is connected with another bonding pad 114, on the semiconductor chip 112, positioned on the opposite side with respect to the X–X′ direction, through the bonding wire 116, the bonding wire would crosse and then make short circuits with another bonding wires.
However, in order to make an electrical connection between the circuit on the mother board and the electric component positioned on the mother board, a practical requirement still exists in which, for example, the bonding pad 1141 on the semiconductor chip 112 is connected with the bonding pad 1045 on the circuit board 102. This can be attained by changing the circuit pattern in the semiconductor chips 110 and 12 according to the circuit patterns of the mother boards, which disadvantageously requires a variety of exposure masks for the circuits of the chips.